1. Field of the Invention
The present invention relates to a method and a circuit for timing dynamic reading of a memory cell with control of the integration time.
2. Description of the Related Art
As is known, the need for nonvolatile memories having increasingly larger densities has led to manufacturing multi-level memories wherein the information, stored as charge quantity in a floating-gate region, is encoded by fractioning the entrapped charge. In this way, the characteristic of a multilevel flash cell is described by a number of curves representing the pattern of the drain current Ids as a function of the gate voltage Vgs, each curve being associated to a different logic value. For examples FIG. 1 shows the characteristic of a four-level (2-bit) flash cell which stores the bits xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d,xe2x80x9c01xe2x80x9d, and xe2x80x9c00xe2x80x9d, corresponding to threshold voltages Vt1, Vt2, Vt3 and Vt4.
Reading of multi-level cells is carried out evaluating the current or the voltage.
Current reading is based on comparing the current flowing in a cell at a preset gate voltage Vgs and the current flowing in a reference cell, the characteristic of which is intermediate between the distributions of the programmed cells, as shown in FIG. 2. The comparison is made after a current-to-voltage conversion, both of the current of the cell and of the reference current.
Current reading has a number of problems, the main ones depend on parasitic resistances, such as source and drain-contact resistance of the cell, resistance of the metal connections, and resistance caused by the pass transistors of the column decoder.
As a whole, the result is a reduction in current dynamics. Consequently, the comparator that compares the voltages after current-to-voltage conversion must have a greater sensitivity. In addition, the actual characteristics differ with respect to the ideal ones, as shown in FIG. 3. Due to such non-idealities, current reading of multilevel memory cells having more than two bits per cell is difficult, because it is required to distinguish extremely close current levels from one another.
To overcome the above problems, U.S. Pat. No. 6,034,888, in the name of the present Applicant, proposes a voltage reading method using a closed-loop circuit (see FIG. 4). In this circuit, the current of the cell to be read is compared with a reference current, and the gate voltage of the cell is modulated until reaching the equilibrium of the system. Thereby, the gate voltage of the cell reaches a value that can be defined as the threshold value of the cell.
However, also this solution is not free from problems, due to the need for an A/D converter able to read the voltage on the gate terminal of the cell, and to the constraint of not being able to read more than one cell at a time, since the row is in common to more than one cell and cannot assume different voltage values.
The solutions devised for solving the above problems moreover involve other disadvantages (increase in read time, greater area) and in any case call for the capacity to discriminate very small currents. On the other hand, the new technologies, involving a reduction in the cell dimensions, lead in turn to a reduction in the cell current, even though solutions are known for reducing the parasitic effects that determine the losses of linearity.
More recently, a dynamic reading of memory cells has been proposed, as described in European Patent Application N. 01830017.8 of Jan. 15, 2001, in the name of the present Applicant. Such proposal, which is based on time integration of the electric charge supplied to a memory cell to be read through a charging step or a discharging step of a capacitive element, will be hereinafter discussed, with reference to FIGS. 5 and 6.
In FIG. 5, a memory cell is represented by a current source 10, which is connected between a ground line or connectionxe2x80x94hereinafter referred to as ground line 19xe2x80x94and a charge-transfer node 11. The current source 10 has a control node 10a receiving a first control signal s and absorbs a constant current I directed towards the ground line 19, when enabled by the first control signal s. The charge-transfer node 11 is connected to a reading circuit 20 comprising a decoupling stage 21, a charge-regeneration capacitor 22 having a capacitance Ca, and an integration capacitor 23 having a capacitance Cb.
In detail, the decoupling stage 21, formed by a circuit known as xe2x80x9ccascodexe2x80x9d, comprises an inverting element, here an inverter 24, having an input connected to the charge-transfer node 11 and an output connected to the gate terminal of a cascode transistor 25, of NMOS type. The cascode transistor 25 moreover has a source terminal connected to the charge-transfer node 11 and a drain terminal connected to the drain terminal of a pass transistor 27, of NMOS type. The pass transistor 27 has a gate terminal receiving a second control signal Vp and a drain terminal connected to a charge-integration node 28.
The charge-regeneration capacitor 22 has a first terminal 22a connected to the charge-integration node 28 and a second terminal 22b connected to the ground line 19. The charge-integration node 28 is connected to the drain terminal of a charge transistor 29, of PMOS type. The charge transistor 29 has a source terminal connected to a biasing line 30 set at a bias voltage Vpcx and a gate terminal receiving a charge-enabling signal en. The bias voltage Vpcx can be either a standard supply voltage (e.g. of 3 V) or a boosted voltage (e.g,. of 6 V) provided by a boosting device of a known type and not shown herein.
Finally, the charge-integration node 28 forms the output of the reading circuit 20, and generates a voltage Va proportional, as will be explained hereinafter, to the current I flowing in the current source 10. A voltage Vb is present on the charge-transfer node 11.
Operation of the circuit of FIG. 5 is the following (see also FIGS. 6A-E).
Initially, the voltages Va and Vb on the charge-integration node 28 and on the charge-transfer node 11 are low. The first control signal s keeps the current source 10 off. In addition, the charge-enabling signal en is low and keeps the charge transistor 29 on. The second control signal Vp is high and keeps the pass transistor 27 on. In this condition, the output of the inverter 24 is high, and the cascode transistor 25 is on and enables charging of the integration capacitor 23 up to the threshold voltage of the inverter 24. As soon as the voltage Vb on the charge-transfer node 11 has reached the triggering voltage of the inverter 24, the latter switches and turns off the cascode transistor 25, which interrupts charging of the integration capacitor 23. In addition, the charge-regeneration capacitor 22 charges up to the bias voltage (i.e., until Va=Vpcx).
In steady-state conditions, at the end of charging, the following relations apply:
Vai=Vpcx 
Qai=CaVai=CaVpcx 
Qbi=CbVbi 
where Vai is the value of the voltage Va at the end of the charging step, Qai is the charge stored in the charge-regeneration capacitor 22, Vbi is the value of the voltage Vb at the end of the charging step, and Qbi is the charge stored in the integration capacitor 23.
At the instant t1, the charge-enabling signal en switches to the high state (Vpcx) and turns off the charge transistor 29 (in this way isolating the charge-regeneration capacitor 22 from the supply line 30). Next (instant t2), the second control signal Vp switches to low and turns off the pass transistor 27 (thereby isolating the charge-transfer node 11 and the charge-integration node 28). Finally (instant t3), the first control signal s switches and turns on the current source 10, which, to a first approximation, goes to a steady-state condition in a negligibly small time, so that the integration capacitor 23 will not be affected by current transients.
Consequently, the integration capacitor 23 discharges linearly, supplying the constant current I to the current source 10 through the charge-transfer node 11. At the instant t4, the control signal s switches again and turns off the current source 10, thus interrupting the discharging step. In practice, if xcex94t=t4xe2x88x92t3 is the time interval when the current source 10 is on, xcex94Vb is the voltage variation on the charge-transfer node 11 for the time interval xcex94t, and xcex94Qb is the charge supplied to the current source 10, i.e., the charge lost by the integration capacitor 23, we have
Va,t3=Vpcx 
  I  =            C      b        ⁢                  Δ        ⁢                  xe2x80x83                ⁢                  V          b                            Δ        ⁢                  xe2x80x83                ⁢        t            xe2x80x83Ixcex94t=Cbxcex94Vb=xcex94Qb       Δ    ⁢          xe2x80x83        ⁢          V      b        =                    I        ⁢                  xe2x80x83                ⁢        Δ        ⁢                  xe2x80x83                ⁢        t                    C        b              =                  Δ        ⁢                  xe2x80x83                ⁢                  Q          b                            C        b            
For example, with Ca=0.5 pF and Cb=5 pF, the time interval xcex94t when discharging of the integration capacitor 23 takes place is about 60 nsec.
Next (instant t5), the second control signal Vp switches again to high, turning on the pass transistor 27 and connecting together, through the decoupling stage 21, the charge-integration node 28 and the charge-transfer node 11. Consequently, the charge-regeneration capacitor 22 discharges rapidly to the integration capacitor 23, re-integrating the charge lost by the latter, according to a charge-sharing process. In practice, the charge-regeneration capacitor 22 operates as a charge reservoir. However, the charge-integration node 28 and the charge-transfer node 11 do not assume the same potential. In fact, the decoupling stage 21 allows the charge-transfer node 11 to reach only the value of the triggering voltage of the inverter 24, after which the inverter 24 turns on the cascode transistor 25, thus once again isolating the charge-integration node 28 from the charge-transfer node 11. The charge-integration node 28, instead, goes to a voltage value Vaf given by the capacitive sharing between the integration capacitor 23 and the charge-regeneration capacitor 22 (charge-sharing step).
At the end, in steady-state conditions, the final voltage on the charge-regeneration capacitor 22 is equal to Vaf, the final charge of the charge-regeneration capacitor 22 is equal to Qaf, and the charge transferred from the charge-regeneration capacitor 22 to the integration capacitor 23 is xcex94Qa, equal to the charge xcex94Qb lost by the charge-regeneration capacitor (which has returned to the initial conditions). Consequently, we have
Vbf=Vbi 
      V          a      ,      f        =                    Q        af                    C        a              =                                        Q            ai                    -                      Δ            ⁢                          xe2x80x83                        ⁢                          Q              a                                                C          a                    =                                                  Q              ai                        -                          Δ              ⁢                              xe2x80x83                            ⁢                              Q                b                                                          C            a                          =                                                                              C                  a                                ⁢                                  V                  ai                                            -                              I                ⁢                                  xe2x80x83                                ⁢                Δ                ⁢                                  xe2x80x83                                ⁢                t                                                    C              a                                =                                                                      C                  a                                ⁢                Vp                ⁢                                  xe2x80x83                                ⁢                c                ⁢                                  xe2x80x83                                ⁢                x                            -                              I                ⁢                                  xe2x80x83                                ⁢                Δ                ⁢                                  xe2x80x83                                ⁢                t                                                    C              a                                          
and hence                               V                      a            ,            f                          =                              V                          p              ⁢                              xe2x80x83                            ⁢              c              ⁢                              xe2x80x83                            ⁢              x                                -                                    I              ⁢                              xe2x80x83                            ⁢              Δ              ⁢                              xe2x80x83                            ⁢              t                                      C              a                                                          (        1        )            
In practice, there exists a linear relation between the final voltage Va on the charge-integration node 28 and the current absorbed by the current source 10. Consequently, integrating the current absorbed by the current source 10 in a preset time interval (integration time xcex94t), the voltage Va on the charge-integration node 28 is proportional to the current I. Consequently, by appropriately sizing the integration time xcex94t and the capacitance Ca, the value of the current I, even if very small, can be converted into a voltage value (voltage Va) having an amplitude that may be read with present-day current circuits.
In addition, from Equation (1) it is possible to calculate the variation xcex94Va of the voltage Va on the charge-integration node 28 generated by variations xcex94I of the current of the current source 10. In fact, from Equation (1) it is                                           Δ            ⁢                          xe2x80x83                        ⁢                          V              a                                            Δ            ⁢                          xe2x80x83                        ⁢            I                          =                  -                                    Δ              ⁢                              xe2x80x83                            ⁢              t                                      C              a                                                          (        2        )            
Relation (2) makes it possible to distinguish very small current variations from one another by measuring the voltage difference xcex94Va that may be obtained on the charge-integration node 28.
For example, setting xcex94t=50 ns, if a variation xcex94Va of 100 mV is desired for a current variation xcex94I=1 xcexcA, we obtain       C    a    =                              Δ          ⁢                      xe2x80x83                    ⁢          I                          Δ          ⁢                      xe2x80x83                    ⁢                      V            af                              ⁢      Δ      ⁢              xe2x80x83            ⁢      t        =          0.5      ⁢              xe2x80x83            ⁢      p      ⁢              xe2x80x83            ⁢      F      
If it is desired a reduction of the voltage Vb on the charge-transfer node 11 of 0.5 V in 50 ns for a maximum current of 50 xcexcA (which is assumed as being the maximum of the dynamics for the memory cell represented schematically by the current source 10), we have       C    b    =                    I        ⁢                  xe2x80x83                ⁢        Δ        ⁢                  xe2x80x83                ⁢        t                    Δ        ⁢                  xe2x80x83                ⁢                  V          b                      =          5      ⁢              xe2x80x83            ⁢      p      ⁢              xe2x80x83            ⁢      F      
With this sizing we then obtain that, for each xcexcA of variation in the current I of the current source 10, the voltage Va on the charge-integration node 28 varies by 100 mV, which can be detected without any problems.
In the European patent application referred to above it is moreover demonstrated that the source 10 is equivalent to a nonvolatile memory cell which may be connected to and disconnected from the charge-transfer node 11 through the column decoder (which receives the control signal s) and a further cascode circuit.
The read circuit described above thus enables discrimination, in a short time, of programming states that are very close to one another, in practice enabling increase in the number of bits that may be stored in a cell (for example, four bits, corresponding to 16 programming levels), but has a number of drawbacks. It is known, in fact, that, given the same programming level, the current flowing in a nonvolatile memory cell depends upon a plurality of factors, both external factors (e.g., temperature) and process factors. Consequently, also the charge xcex94Qb supplied by the integration capacitor 23 to the current generator 10 and the voltage Va on the charge-regeneration node 28 at the end of the charge-sharing step are not constant, but depend upon the external factors and process factors themselves by means of the current I, as shown by the above-mentioned relation
xcex94Qb=Ixcex94t 
as well as upon relation (1).
In practice, as the process conditions, the biasing voltage and the temperature vary, it is not possible to guarantee that the result of the charge-regeneration step will be constant, or, in other words, that the charge xcex94Qb lost by the integration capacitor 23 at the end of the interval xcex94t, and hence the voltage Va on the charge-integration node 28, will remain constant whenever a cell having a given programming level is read.
On the other hand, possible variations in the voltage Va deriving therefrom may cause reading errors. For example, if the current carried by the cells increases, the charge xcex94Qb lost by the integration capacitor 23 may happen to be greater than the charge that is altogether present on the restore capacitor or charge-regeneration capacitor 22. In this case, the charge-regeneration capacitor 22 discharges completely without being able to replace altogether the charge xcex94Qb lost by the integration capacitor 23, and hence certain programming levels (in particular those to which there correspond lower threshold voltages and higher cell currents) may become indistinguishable from one another.
An embodiment of the present invention provides a read-timing circuit that will enable the limitations described above to be overcome.
In an embodiment of the present invention, a method and a circuit for timing dynamic reading of a memory cell are provided wherein the device has a first capacitive element connected to a memory cell and supplies a first constant current when the memory cell is activated and activation and control elements for activating the memory cell for a controlled time interval such as to compensate for deviations of a first current from a nominal value.